This invention relates to semiconductor devices, and more particularly to clock generator circuits of the type used in CMOS VLSI dynamic memory devices.
Semiconductor memory devices of the dynamic read/write type employ a large number of internal clocks, which must drive large capacitive loads; the clock generator circuits used for this purpose are an important factor in determining the speed and power dissipation of the devices. An NMOS dynamic RAM of the 64K-bit size is illustrated in U.S. Pat No. 4,239,993 issued to McAlexander, White and Rao, and a clock generator used in such device is illustrated in U.S. Pat. No. 4,239,992, issued to Hong and Redwine, both patents asigned to Texas Instruments. In constructing a similar dynamic RAM in CMOS technology, and at higher bit density (such as 256K-bit or 1-Megabit), the necessity for low power dissipation and other such design constraints become more stringient.
It is the principal object of this invention to provide improved clock generator circuits for semiconductor integrated circuits such as memory devices, particularly devices made by CMOS processes. Another object is to provide an improved CMOS clock generator which operates from a simplified clock arrangement, which does not dissipate static power, in which the clock speed is not determined by charging of capacitors, in which unwanted excersions of the output voltage are avoided, in which a boosted voltage drives the output transistor, and in which impact ionization current is reduced.